Non-volatile memory structure and corresponding manufacturing process

ABSTRACT

A semiconductor non-volatile memory device that includes memory cells and selection transistors. The memory cells each include a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, and each of the floating gate transistors is serially coupled to one of the selection transistors. A contact to the control gate is located above the active area. In a preferred embodiment, the contact is substantially aligned with a central portion of the active area. A method for manufacturing a non-volatile memory device on a semiconductor substrate is also provided. According to the method, a poly1 layer is deposited, an interpoly dielectric layer is deposited above the poly1 layer, and a poly2 layer is deposited above the interpoly dielectric layer. A mask is provided to define the control gate, and a Self-Aligned poly2/interpoly/poly1 stack etching is used to define a gate stack structure that includes the control gate and the floating gate. The floating gate is defined using only the mask and the Self-Aligned poly2/interpoly/poly1 stack etching. In one preferred method, a contact to the control gate is formed above the active area.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims priority from prior European Patent Application No. 98-202563.7, filed Jul. 30, 1998, the entire disclosure of which is herein incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to semiconductor memory devices, and more specifically to a non-volatile semiconductor memory device having memory cells that each include a floating gate transistor serially connected to a selection transistor and a process for manufacturing the same.

[0004] 2. Description of Related Art

[0005] The memory cells of a conventional non-volatile semiconductor memory device each include a floating gate transistor having an active area, source/drain regions, and a control gate coupled to a floating gate. The floating gate transistor is serially connected to a selection transistor. Double-poly technology is widely used in the manufacturing of such non-volatile memory devices (e.g., EPROMs, EEPROMs, or Flash-EEPROMs) to realize the floating gate transistors.

[0006] Conventionally, in order to realize a memory device including non-volatile memory cells in a double-poly technology, it is necessary to use a set of standard CMOS process masks that include at least the following masks: POLY1 mask for defining the floating gates, MATRIX (or interpoly dielectric) mask to remove the interpoly dielectric protection of the memory array, and POLY2 (or control gates) mask for defining the poly lines that form the control gates of the memory cells. Other masks are usually also necessary for manufacturing a specific kind of non-volatile memory cell. For example, a specific mask for N+ implant is required for EEPROMs, implant masks are required for source and/or drain junction engineering in Flash-EEPROMs, and a Self-Aligned-Source mask is used to obtain a source diffusion aligned to the polysilicon lines.

[0007] Because the mask count is a cost issue for economic production, and also because the increasing number of metallization levels required for interconnections is impacting the cycle-time in the production line, it is desirable to reduce the number of masks required to realize a non-volatile memory cell, while at the same time maintaining the same cell features. However, a problem specifically related to the manufacturing of non-volatile memory cells with a compact layout concerns the POLY1 mask. With reference to FIGS. 1A through 1D, the POLY1 mask is used to cross the active area on the diffusion region used as a source line for the memory array.

[0008] The floating gates must be defined in a direction that is parallel to the word lines, and this is obtained by etching the poly1 layer with a sufficient extension beyond the future control gate line. In this manner, assuming a “self-aligned” process, any short between floating gates of adjacent cells is avoided when the floating gate is defined in the other direction by the poly2/interpoly/poly1 stack etching. Therefore, in the regions in which POLY1 crosses the active areas, no poly1 layer is left on the active area and during the stack etching a consistent substrate etching is provided by the trench 20, as shown in FIG. 1B. This substrate etching is unavoidable because poly2 etching can be stopped on interpoly dielectric, while the interpoly dielectric etch is stopped on poly1, but in the overlapping regions poly1 is not present and the etching is stopped only on the active area.

[0009] As a result, the interpoly dielectric etching is stopped on the silicon substrate, but during the poly1 etching the substrate is also etched. For this reason, the source line will not be flat and, even if this is not a severe problem because an N+ implant for source and drain can guarantee the electrical continuity of the source line, there is a serious drawback in that the source resistance is increased as compared to a typical N+ diffusion of a flat cross section. Moreover, if the manufacturing process includes a phase of active area salicidation (as in most advanced technologies now used) the source line irregularity can cause further problems due to reaction of the metal (i.e., Ti) with silicon. More particularly, the metal reaction involves regions with a low doping concentration (e.g., the bottom corner of the etched source line portion), so a short between the N+ diffused substrate region can occur.

[0010] The problem of silicon etching in the source line and the corresponding increase in the source resistance is particularly severe in the case of EEPROM memory devices for which the bits of the same byte must be adjacent for construction. Moreover, the control gates are separated at byte level in order to allow byte granularity both in write and erase phases. The inability to divide the bits leads to an enhanced series resistance effect during the reading phase, because all the bits of the same byte can drain current and a correspondingly increased voltage drop on the source line occurs. The only possible solution that has been proposed is to introduce more frequent source contacts. However, this causes a corresponding overall circuit area increase of the memory device.

SUMMARY OF THE INVENTION

[0011] In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a solution to any problems related to the substrate etching in the source line. Such problems can be of a technological nature if related to salicidation or of an electrical nature if related to excessive source line resistivity.

[0012] Another object of the present invention is to provide a memory structure having control gate lines with an intrinsic low resistivity. The control gate line resistance related to the poly2 layer sheet resistivity is very important to reduce the access resistance, and therefore the access time to the memory array.

[0013] A further object of the present invention is to provide a memory structure that allows a cell area reduction without the need for a Self-Aligned-Source mask and, at the same time, avoids the problem of potential dielectric breakdown between control gate line and source diffusion. Memory devices manufactured without a Self-Aligned-Source process and with an extra dedicated mask require a sufficient distance between the poly2 control gate and the source active area, otherwise the control gate line can be directly overlapped on the diffusion with only interposition of the interpoly dielectric layer where the poly1 has been removed. Because high voltages are necessary during memory programming phases, there is a breakdown risk for this dielectric layer that can lead to a device failure.

[0014] In accordance with preferred embodiments of the present invention, the POLY1 mask is eliminated from the manufacturing process and the floating gates are defined using only a POLY2 mask and a Self-Aligned Poly2/interpoly/Poly1 stack etching. The control gate line is preferably realized by a metal interconnection that is electrically connected to the second polysilicon layer, which represents the physical control gate, and a contact is preferably provided on the control gate over the active area.

[0015] One embodiment of the present invention provides a semiconductor nonvolatile memory device that includes memory cells and selection transistors. The memory cells each include a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, and each of the floating gate transistors is serially coupled to one of the selection transistors. A contact to the control gate is located above the active area. In a preferred embodiment, the contact is substantially aligned with a central portion of the active area.

[0016] Another embodiment of the present invention provides a method for manufacturing a non-volatile memory device on a semiconductor substrate. The memory device includes memory cells arranged in a memory array, and each of the memory cells has a floating gate transistor serially coupled to a selection transistor. The floating gate transistor includes an active area, source and drain regions, a floating gate, and a control gate. According to the method, a poly1 layer is deposited, an interpoly dielectric layer is deposited above the poly1 layer, and a poly2 layer is deposited above the interpoly dielectric layer. A mask is provided to define the control gate, and a Self-Aligned poly2/interpoly/poly1 stack etching is used to define a gate stack structure that includes the control gate and the floating gate. The floating gate is defined using only the mask and the Self-Aligned poly2/interpoly/poly1 stack etching. In one preferred method, a contact to the control gate is formed above the active area.

[0017] Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1A is an enlarged scale cross sectional view of a conventional semiconductor EEPROM memory cell taken along line I-I of FIG. 1C;

[0019]FIG. 1B is a cross sectional view of the semiconductor EEPROM memory cell of FIG. 1A taken along line II-II of FIG. 1C;

[0020]FIG. 1C is a top plan view of the EEPROM memory cell of FIG. 1A;

[0021]FIG. 1D is a cross sectional view of the semiconductor EEPROM memory cell of FIG. 1A taken along line III-III of FIG. 1C;

[0022]FIG. 2A is an enlarged scale cross sectional view of a semiconductor EEPROM memory cell according to a first embodiment of the present invention taken along line I-I of FIG. 2C;

[0023]FIG. 2B is a cross sectional view of the semiconductor EEPROM memory cell of FIG. 2A taken along line lI-II of FIG. 2C;

[0024]FIG. 2C is a top plan view of the EEPROM memory cell of FIG. 2A;

[0025]FIG. 2D is a cross sectional view of the semiconductor EEPROM memory cell of FIG. 2A taken along line III-III of FIG. 2C;

[0026]FIG. 3A is an enlarged scale cross sectional view of a second embodiment of a semiconductor EEPROM memory cell according to the present invention taken along line I-I of FIG. 3C;

[0027]FIG. 3B is a cross sectional view of the semiconductor EEPROM memory cell of FIG. 3A taken along line II-II of FIG. 3C;

[0028]FIG. 3C is a top plan view of the EEPROM memory cell of FIG. 3A;

[0029]FIG. 3D is a cross sectional view of the semiconductor EEPROM memory cell of FIG. 3A taken along line III-III of FIG. 3C;

[0030]FIG. 4A is an enlarged scale cross sectional view of an embodiment of a semiconductor EPROM or Flash-EEPROM memory cell according to the present invention taken along line I-I of FIG. 4C;

[0031]FIG. 4B is a cross sectional view of the semiconductor EPROM or Flash-EEPROM memory cell of FIG. 4A, taken along line II-II of FIG. 4C;

[0032]FIG. 4C is a top plan view of the memory cell of FIG. 4A;

[0033]FIG. 4D is a cross sectional view of the memory cell of FIG. 4A taken along line III-III of FIG. 4C;

[0034]FIGS. 5A, 5B, and 5C are enlarged scale top plan views of a conventional EEPROM memory cell, an embodiment of the present invention, and another embodiment of the present invention, respectively;

[0035]FIGS. 6A and 6B show an enlarged scale layout portion of a semiconductor non-volatile memory device including respectively a source line contact region and a byte switch region realized according to the conventional process;

[0036]FIGS. 7A and 7B show an enlarged scale layout portion of a semiconductor non-volatile memory device including respectively a source line contact region and a byte switch region realized according to an embodiment of the present invention; and

[0037]FIGS. 8A and 8B show an enlarged scale layout portion of a semiconductor non-volatile memory device including respectively a source line contact region and a byte switch region realized according to another embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0038] Preferred embodiments of the present invention will be described in detail hereinbelow with reference to the attached drawings.

[0039]FIGS. 2A, 2B, 2C, and 2D show a non-volatile memory cell according to a first embodiment of the present invention. As shown, the EEPROM memory cell 1 is integrated on a semiconductor substrate 15 of the P type and includes two levels of polysilicon. (While reference will be made in the ensuing description to a preferred embodiment employing devices of the N type, corresponding devices of the P type are formed by simply reversing the types of conductivities mentioned hereinafter.) The memory cell 1 includes a floating gate transistor and an associated selection transistor, which is used for selecting a cell to be programmed from a group of cells in a memory matrix.

[0040] The floating gate transistor includes an active area, a drain region 16, and a source region 17. The active area is delimited by field oxide regions 14, and the drain region 16 is formed by an N-type implant into the substrate 15. The source region 17 of the cell 1 is formed by implanting the substrate 15 with a dopant of the N type. The substrate region 15 provided between the drain 16 and source 17 regions forms the active area channel region 9 of the floating gate transistor. The channel 9 is overlaid by a gate region 2 in an isolated manner with the interposition of an oxide layer 3. The gate region 2 conventionally includes a floating gate and control gate. In particular the gate region 2 includes a stack aligned structure including a tunnel oxide layer 3, a first polysilicon (poly1) layer 4, an interpoly dielectric layer 5, and a second polysilicon (poly2) layer 6.

[0041] In accordance with the present invention, the memory cell 1 is preferably manufactured without a POLY1 mask. The cell layout has been modified as compared to conventional solutions, and the floating gate has been defined in both directions I-I and II-II with the POLY2 mask and the Self-Aligned poly2/interpoly/poly1 stack etching. The cell layout is shown in FIG. 2C. A control gate contact 7 is provided over the second poly2 layer 6. This contact 7 is provided on the gate region 2 over the active area and substantially aligned to the central portion of the channel area 9. A first metallization layer 8 is provided to strap the floating gate transistor of the cell 1 to a selection transistor that is serially connected on the drain side.

[0042] The bit line of the memory array is realized by a second metallization level 10 and by an electrical connection 11 to the drain of the cell 1. More specifically, the electrical connection to the drain 16 of the cell 1 is realized through stacked contact that is active to first metal layer 8 and by a contact via 12 between the first metal layer and the second metal layer 10. A first metal layer island is provided around the contact via 12 with appropriate dimensions to avoid any problem in the case of misalignment.

[0043] Another embodiment of the memory cell according to the present invention is shown in FIGS. 3A, 3B, 3C, and 3D. The main difference between this alternative layout solution and the previous embodiment is that the control gate contact 7 between the second poly2 layer 6 and the first metal layer 8 is placed on the field oxide, not above the active area. In order to obtain this configuration, a poly1 wing 18 and a poly2 wing 19 are provided to define the control gate capacitive coupling of the floating gate transistor. These wings 18 and 19 are asymmetric with respect to the gate active area of the non-volatile memory cell 1. The advantage of this embodiment is that the contact 7 is realized on a flat region. Additionally, the principle of the present invention may be applied to a Flash-EEPROM or to an EPROM cell as shown in FIGS. 4A, 4B, 4C, and 4D.

[0044] The sequence of process phases that are preferably used to obtain either the embodiment of FIG. 2 or the embodiment of FIG. 3 are as follows:

[0045] 1) standard operations of a double-poly CMOS process are provided for non-volatile memories up to poly1 deposition;

[0046] 2) interpoly deposition over the poly1 layer 3;

[0047] 3) a MATRIX mask is used to remove the interpoly dielectric layer 5 outside the memory array;

[0048] 4) poly2 deposition is performed over the whole circuit layout;

[0049] 5) a POLY2 or control gate mask is used to expose and define the control gate regions;

[0050] 6) a polyp2/interpoly/poly1 stack etching is provided to define the gate stack structures of the memory array;

[0051] 7) standard phases are then provided for Source/Drain junction engineering depending on the kind of memory cell, optional salicide formation, interlevel dielectric deposition, contact opening, etc.;

[0052] 8) preferably, no implant in the control gate contacts 7, poly2 to first metal, are performed in order to reduce the danger of excessive contamination and possible interpoly dielectric degradation. (As an alternative, when salicidation steps are provided and no implant in the contact is required, a dedicated mask is always present for implanting N+ dopant just for N-type contacts, and ______ can be generated so that the control gate is protected from the implant; and

[0053] 9) The process steps are then completed in the standard manner.

[0054] Thus, according to the present invention, the POLY1 mask is eliminated from the process steps and the cell layout is modified in order to define the floating gates with only the POLY2 mask and the Self-Aligned Poly2/interpoly/Poly1 stack etching.

[0055] With reference to the example shown in FIG. 5B, a slightly different layout for the memory cell will now be explained. As compared to the first embodiment disclosed above, in this layout the first metal layer of the control gate line has a slightly different shape and does not completely overlap the control gate. Therefore, the metal1 control gate line does not overlap the poly1/poly2 floating gate region, but it presents a lateral extension over the gate region in order to overlap the poly2/metal1 contact. The layout of a conventional solution is also shown in FIG. 5A. The layout shown in FIG. 5B is used to realize a memory array having a more compact structure, as shown in FIGS. 7A, 7B, 8A, and 8B.

[0056] For a better understanding of the present invention, FIGS. 6A and 6B show a layout portion of a conventional solution for an EEPROM memory array in the region in which the source line is contacted and in the region in which a byte is switched, respectively. FIGS. 7A and 7B show a corresponding layout portion of a memory cell according to the first embodiment of the present invention. As shown, more room is available in the region of the byte switch (FIG. 7B) as compared to the conventional solution. While the metal1 control-gate line can be made shorter than the one illustrated in FIG. 6B, the same footprint was kept in order to show the extra space.

[0057]FIGS. 8A and 8B show a corresponding layout portion of a memory cell according to the second embodiment of the present invention. As shown, this embodiment also provides more room both in the region of the byte switch (FIG. 8B) and in the region in which the source is contacted (FIG. 8A). This is due to the asymmetry of the floating gates with respect to bit-line active areas, so the space needed to accommodate the contact on the source is less. The critical rule is the contact distance to the polysilicon. Additionally, in this embodiment, the same footprint as in the conventional solution of FIGS. 6A and 6B has been kept in order to show the extra space.

[0058] While there has been illustrated and described what are presently considered to be the preferred embodiments of the present invention, it will be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from the true scope of the present invention. Additionally, many modifications may be made to adapt a particular situation to the teachings of the present invention without departing from the central inventive concept described herein. Furthermore, an embodiment of the present invention may not include all of the features described above. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the invention include all embodiments falling within the scope of the appended claims. 

What is claimed is:
 1. A semiconductor non-volatile memory device comprising: a plurality of memory cells each including a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, a contact to the control gate being located above the active area; and a plurality of selection transistors, each of the floating gate transistors being serially coupled to one of the selection transistors.
 2. The memory device as defined in claim 1 , wherein the contact is substantially aligned with a central portion of the active area.
 3. The memory device as defined in claim 1 , wherein the floating gate and control gate are formed with double-poly wings that are asymmetric with respect to the active area, and the contact is located above the double-poly wings.
 4. The memory device as defined in claim 1 , wherein the floating gate is defined by only a POLY2 mask and a Self-Aligned poly2/interpoly/poly1 stack etching.
 5. The memory device as defined in claim 1 , wherein the device is a Flash-EEPROM.
 6. A semiconductor non-volatile memory device comprising: a plurality of memory cells each including a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, a contact to the control gate being located above a field oxide region and not above the active area; and a plurality of selection transistors, each of the floating gate transistors being serially coupled to one of the selection transistors.
 7. A semiconductor non-volatile memory device comprising: at least one memory cell including a floating gate transistor that has an active area, source and drain regions, a floating gate, and a control gate; at least one selection transistor serially coupled to the floating gate transistor; and a control gate line formed by at least a first metal interconnection layer, the control gate line being electrically connected to the control gate of the memory cell by a contact that is located above the active area.
 8. The memory device as defined in claim 7 , wherein the contact is substantially aligned with a central portion of the active area.
 9. The memory device as defined in claim 7 , wherein the floating gate and control gate are formed with double-poly wings that are asymmetric with respect to the active area, and the contact is located above the double-poly wings.
 10. The memory device as defined in claim 7 , further comprising a bit line formed by at least a second metal interconnection layer, the bit line being electrically connected to the drain region.
 11. The memory device as defined in claim 10 , wherein the electrical connection of the bit line to the drain region is realized by a stacked contact that is active to the first metal interconnection layer and another contact between the first metal interconnection layer and the second metal interconnection layer.
 12. The memory device as defined in claim I 1, wherein a metal layer island is provided around the other contact.
 13. An information handling system including at least one semiconductor nonvolatile memory device, said memory device comprising: a plurality of memory cells each including a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, a contact to the control gate being located above the active area; and a plurality of selection transistors, each of the floating gate transistors being serially coupled to one of the selection transistors.
 14. The information handling system as defined in claim 13 , wherein the contact is substantially aligned with a central portion of the active area.
 15. The information handling system as defined in claim 13 , wherein the floating gate and control gate are formed with double-poly wings that are asymmetric with respect to the active area, and the contact is located above the double-poly wings.
 16. A method for manufacturing a non-volatile memory device on a semiconductor substrate, the memory device including a plurality of memory cells arranged in a memory array, each of the memory cells having a floating gate transistor serially coupled to a selection transistor, the floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, said method comprising the steps of: depositing a polyl layer; depositing an interpoly dielectric layer above the poly1 layer; depositing a poly2 layer above the interpoly dielectric layer; providing a mask to define the control gate; and using a Self-Aligned poly2/interpoly/poly1 stack etching to define a gate stack structure that includes the control gate and the floating gate, wherein the floating gate is defined using only the mask and the Self-Aligned poly2/interpoly/poly1 stack etching.
 17. The method as defined in claim 16 , further comprising the step of using another mask to remove selected portions of the interpoly dielectric layer before the step of depositing the poly2 layer.
 18. The method as defined in claim 16 , further comprising the step of forming a contact to the control gate above the active area.
 19. The method as defined in claim 18 , wherein the contact is substantially aligned with a central portion of the active area.
 20. The method as defined in claim 16 , further comprising the step of: forming a contact to the control gate, wherein the floating gate and control gate are formed with double-poly wings that are asymmetric with respect to the active area, and the contact is located above the double-poly wings.
 21. The method as defined in claim 16 , further comprising the step of forming a contact to the control gate, the contact being located above a field oxide region and not above the active area. 